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d a t a sh eet product speci?cation supersedes data of 1998 jun 04 2003 jun 25 integrated circuits 74hc595; 74hct595 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
2003 jun 25 2 philips semiconductors product speci?cation 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74hc595; 74hct595 features 8-bit serial input 8-bit serial or parallel output storage register with 3-state outputs shift register with direct clear 100 mhz (typical) shift out frequency esd protection: hbm eia/jesd22-a114-a exceeds 2000 v mm eia/jesd22-a115-a exceeds 200 v. applications serial-to-parallel data conversion remote control holding register. description the 74hc/hct595 are high-speed si-gate cmos devices and are pin compatible with low power schottky ttl (lsttl). they are specified in compliance with jedec standard no. 7a. the 74hc/hct595 is an 8-stage serial shift register with a storage register and 3-state outputs. the shift register and storage register have separate clocks. data is shifted on the positive-going transitions of the sh_cp input. the data in each register is transferred to the storage register on a positive-going transition of the st_cp input. if both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register. the shift register has a serial input (ds) and a serial standard output (q7) for cascading. it is also provided with asynchronous reset (active low) for all 8 shift register stages. the storage register has 8 parallel 3-state bus driver outputs. data in the storage register appears at the output whenever the output enable input (oe) is low. quick reference data gnd = 0 v; t amb =25 c; t r =t f = 6 ns. notes 1. c pd is used to determine the dynamic power dissipation (p d in m w). p d =c pd v cc 2 f i n+ s (c l v cc 2 f o ) where: f i = input frequency in mhz; f o = output frequency in mhz; c l = output load capacitance in pf; v cc = supply voltage in volts; n = total load switching outputs; s (c l v cc 2 f o ) = sum of the outputs. 2. for 74hc595 the condition is v i = gnd to v cc . for 74hct595 the condition is v i = gnd to v cc - 1.5 v. symbol parameter conditions typical unit 74hc 74hct t phl /t plh propagation delay c l = 50 pf; v cc = 4.5 v sh_cp to q7 19 25 ns sh_cp to qn 20 24 ns mr to q7 100 52 ns f max maximum clock frequency sh_cp and st_cp 100 57 mhz c i input capacitance 3.5 3.5 pf c pd power dissipation capacitance per package notes 1 and 2 115 130 pf
2003 jun 25 3 philips semiconductors product speci?cation 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74hc595; 74hct595 function table see note 1. note 1. h = high voltage level; l = low voltage level; - = low-to-high transition; = high-to-low transition; z = high-impedance off-state; n.c. = no change; x = dont care. ordering information input output function sh_cp st_cp oe mr ds q7 qn x x l l x l n.c. a low level on mr only affects the shift registers x - l l x l l empty shift register loaded into storage register x x h l x l z shift register clear; parallel outputs in high-impedance off-state - x l h h q6 n.c. logic high level shifted into shift register stage 0; contents of all shift register stages shifted through, e.g. previous state of stage 6 (internal q6) appears on the serial output (q7) x - l h x n.c. qn contents of shift register stages (internal qn) are transferred to the storage register and parallel output stages -- l h x q6 qn contents of shift register shifted through; previous contents of the shift register is transferred to the storage register and the parallel output stages type number package temperature range pins package material code 74hc595n - 40 to +125 c 16 dip16 plastic sot38-4 74hct595n - 40 to +125 c 16 dip16 plastic sot38-4 74hc595d - 40 to +125 c 16 so16 plastic sot109-1 74HCT595D - 40 to +125 c 16 so16 plastic sot109-1 74hc595db - 40 to +125 c 16 ssop16 plastic sot338-1 74HCT595Db - 40 to +125 c 16 ssop16 plastic sot338-1 74hc595pw - 40 to +125 c 16 tssop16 plastic sot403-1 74hct595pw - 40 to +125 c 16 tssop16 plastic sot403-1 74hc595bq - 40 to +125 c 16 dhvqfn16 plastic sot763-1 74hct595bq - 40 to +125 c 16 dhvqfn16 plastic sot763-1
2003 jun 25 4 philips semiconductors product speci?cation 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74hc595; 74hct595 pinning pin symbol description 1 q1 parallel data output 2 q2 parallel data output 3 q3 parallel data output 4 q4 parallel data output 5 q5 parallel data output 6 q6 parallel data output 7 q7 parallel data output 8 gnd ground (0 v) 9 q7 serial data output 10 mr master reset (active low) 11 sh_cp shift register clock input 12 st_cp storage register clock input 13 oe output enable (active low) 14 ds serial data input 15 q0 parallel data output 16 v cc positive supply voltage handbook, halfpage q1 q2 q3 q4 q5 q6 q7 q7' q0 ds gnd st_cp sh_cp v cc oe 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 595 mla001 mr fig.1 pin configuration dip16, so16 and (t)ssop16. handbook, halfpage 116 gnd (1) q1 v cc 8 2 3 4 5 7 q2 q3 q4 q5 q6 15 14 13 12 10 611 9 gnd top view mbl893 q7 q7' mr sh_cp st_cp oe ds q0 fig.2 pin configuration dhvqfn16. (1) the die substrate is attached to this pad using conductive die attach material. it can not be used as a supply pin or input.
2003 jun 25 5 philips semiconductors product speci?cation 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74hc595; 74hct595 handbook, halfpage oe mr 9 15 1 2 3 4 5 6 7 13 10 14 11 12 mla002 q1 q0 q2 q3 q4 q5 q6 q7 q7' ds st_cp sh_cp fig.3 logic symbol. handbook, halfpage msa698 15 9 1 2 3 4 5 6 7 1d 2d c1/ 10 11 14 c2 12 13 en3 srg8 r 3 oe mr q1 q0 q2 q3 q4 q5 q6 q7 q7' ds st_cp sh_cp fig.4 iec logic symbol. handbook, full pagewidth st_cp ds sh_cp mr q7' 8-stage shift register 8-bit storage register 14 11 10 12 9 oe 3-state outputs q1 q2 q3 q5 q6 q7 q4 q0 15 1 2 3 4 5 6 7 13 mla003 fig.5 functional diagram.
2003 jun 25 6 philips semiconductors product speci?cation 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74hc595; 74hct595 handbook, full pagewidth stage 0 stages 1 to 6 stage 7 ff0 d cp q r latch d cp q ff7 d cp q r latch d cp q mla010 dq q1 q2 q3 q4 q5 q6 q7 q7' q0 ds st_cp sh_cp oe mr fig.6 logic diagram.
2003 jun 25 7 philips semiconductors product speci?cation 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74hc595; 74hct595 handbook, full pagewidth high-impedance off-state st_cp ds sh_cp mr oe q1 q0 q7' q6 q7 mla005-1 fig.6 timing diagram.
2003 jun 25 8 philips semiconductors product speci?cation 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74hc595; 74hct595 recommended operating conditions limited values in accordance with the absolute maximum rating system (iec 60134); voltages are referenced to gnd (ground = 0 v). note 1. for dip16 packages: above 70 c derate linearly with 12 mw/k. for so16 packages: above 70 c derate linearly with 8 mw/k. for ssop16 packages: above 60 c derate linearly with 5.5 mw/k. for tssop16 packages: above 60 c derate linearly with 5.5 mw/k. for dhvqfn16 packages: above 60 c derate linearly with 4.5 mw/k. symbol parameter conditions 74hc 74hct unit min. typ. max. min. typ. max. v cc supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 v v i input voltage 0 - v cc 0 - v cc v v o output voltage 0 - v cc 0 - v cc v t amb ambient temperature - 40 - +125 - 40 - +125 c t r ,t f input rise and fall time v cc = 2.0 v -- 1000 --- ns v cc = 4.5 v - 6.0 500 - 6.0 500 ns v cc = 6.0 v -- 400 --- ns symbol parameter conditions min. max. unit v cc supply voltage - 0.5 +7.0 v i ik input diode current v i < - 0.5 v to v i >v cc + 0.5 v - 20 ma i ok output diode current v o < - 0.5 v to v o >v cc + 0.5 v - 20 ma i o output source or sink current v o = - 0.5 v to v cc + 0.5 v q7 standard output - 25 ma qn bus driver outputs - 35 ma i cc , i gnd v cc or gnd current - 70 ma t stg storage temperature - 65 +150 c p tot power dissipation t amb = - 40 to +125 c; note 1 - 500 mw
2003 jun 25 9 philips semiconductors product speci?cation 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74hc595; 74hct595 dc characteristics type 74hc at recommended operating conditions; voltages are referenced to gnd (groun d=0v). symbol parameter test conditions min. typ. max. unit other v cc (v) t amb = - 40 to +85 c ; note 1 v ih high-level input voltage 2.0 1.5 1.2 - v 4.5 3.15 2.4 - v 6.0 4.2 3.2 - v v il low-level input voltage 2.0 - 0.8 0.5 v 4.5 - 2.1 1.35 v 6.0 - 2.8 1.8 v v oh high-level output voltage v i =v ih or v il all outputs i o = - 20 m a 2.0 1.9 2.0 - v 4.5 4.4 4.5 - v 6.0 5.9 6.0 - v q7 standard output i o = - 4.0 ma 4.5 3.84 4.32 - v i o = - 5.2 ma 6.0 5.34 5.81 - v qn bus driver outputs i o = - 6.0 ma 4.5 3.84 4.32 - v i o = - 7.8 ma 6.0 5.34 5.81 - v v ol low-level output voltage v i =v ih or v il all outputs i o =20 m a 2.0 - 0 0.1 v 4.5 - 0 0.1 v 6.0 - 0 0.1 v q7 standard output i o = 4.0 ma 4.5 - 0.15 0.33 v i o = 5.2 ma 6.0 - 0.16 0.33 v qn bus driver outputs i o = 6.0 ma 4.5 - 0.16 0.33 v i o = 7.8 ma 6.0 - 0.16 0.33 v i li input leakage current v i =v cc or gnd 6.0 -- 1.0 m a i oz 3-state output off-state current v i =v ih or v il ; v o =v cc or gnd 6.0 -- 5.0 m a i cc quiescent supply current v i =v cc or gnd; i o =0 6.0 -- 80 m a
2003 jun 25 10 philips semiconductors product speci?cation 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74hc595; 74hct595 note 1. all typical values are measured at t amb =25 c. t amb = - 40 to +125 c v ih high-level input voltage 2.0 1.5 -- v 4.5 3.15 -- v 6.0 4.2 -- v v il low-level input voltage 2.0 -- 0.5 v 4.5 -- 1.35 v 6.0 -- 1.8 v v oh high-level output voltage v i =v ih or v il all outputs i o = - 20 m a 2.0 1.9 -- v 4.5 4.4 -- v 6.0 5.9 -- v q7 standard output i o = - 4.0 ma 4.5 3.7 -- v i o = - 5.2 ma 6.0 5.2 -- v qn bus driver outputs i o = - 6.0 ma 4.5 3.7 -- v i o = - 7.8 ma 6.0 5.2 -- v v ol low-level output voltage v i =v ih or v il all outputs i o =20 m a 4.5 -- 0.1 v q7 standard output i o = 4.0 ma 4.5 -- 0.4 v qn bus driver outputs i o = 6.0 ma 4.5 -- 0.4 v i li input leakage current v i =v cc or gnd 5.5 -- 1.0 m a i oz 3-state output off-state current v i =v ih or v il ; v o =v cc or gnd 5.5 -- 10.0 m a i cc quiescent supply current v i =v cc or gnd; i o =0 5.5 -- 160 m a symbol parameter test conditions min. typ. max. unit other v cc (v)
2003 jun 25 11 philips semiconductors product speci?cation 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74hc595; 74hct595 type 74hct at recommended operating conditions; voltages are referenced to gnd (groun d = 0 v); t r =t f = 6 ns; c l =50pf. symbol parameter test conditions min. typ. max. unit other v cc (v) t amb = - 40 to +85 c; note 1 v ih high-level input voltage 4.5 to 5.5 2.0 1.6 - v v il low-level input voltage 4.5 to 5.5 - 1.2 0.8 v v oh high-level output voltage v i =v ih or v il all outputs i o = - 20 m a 4.5 4.4 4.5 - v q7 standard output i o = - 4.0 ma 4.5 3.84 4.32 - v qn bus driver outputs i o = - 6.0 ma 4.5 3.7 4.32 - v v ol low-level output voltage v i =v ih or v il all outputs i o =20 m a 4.5 - 0 0.33 v q7 standard output i o = 4.0 ma 4.5 - 0.15 0.33 v qn bus driver outputs i o = 6.0 ma 4.5 - 0.16 0.33 v i li input leakage current v i =v cc or gnd 5.5 -- 1.0 m a i oz 3-state output off-state current v i =v ih or v il ; v o =v cc or gnd 5.5 -- 5.0 m a i cc quiescent supply current v i =v cc or gnd; i o =0 5.5 -- 80 m a d i cc additional supply current per input v i =v cc - 2.1 v; i o = 0; note 2 4.5 to 5.5 - 100 450 m a
2003 jun 25 12 philips semiconductors product speci?cation 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74hc595; 74hct595 notes 1. all typical values are measured at t amb =25 c. 2. the value of additional quiescent supply current ( d i cc ) for a unit load of 1 is given here. to determine d i cc per input, multiply this value by the unit load coefficient per input pin: a. pin ds: 0.25 b. pins mr, sh_cp, st_cp and oe: 1.50. t amb = - 40 to +125 c v ih high-level input voltage 4.5 to 5.5 2.0 -- v v il low-level input voltage 4.5 to 5.5 -- 0.8 v v oh high-level output voltage v i =v ih or v il all outputs i o = - 20 m a 4.5 4.4 -- v q7 standard output i o = - 4.0 ma 4.5 3.7 -- v qn bus driver outputs i o = - 6.0 ma 4.5 3.7 -- v v ol low-level output voltage v i =v ih or v il all outputs i o =20 m a 4.5 -- 0.1 v q7 standard output i o = 4.0 ma 4.5 -- 0.4 v qn bus driver outputs i o = 6.0 ma 4.5 -- 0.4 v i li input leakage current v i =v cc or gnd 5.5 -- 1.0 m a i oz 3-state output off-state current v i =v ih or v il ; v o =v cc or gnd 5.5 -- 10.0 m a i cc quiescent supply current v i =v cc or gnd; i o =0 5.5 -- 160 m a d i cc additional supply current per input v i =v cc - 2.1 v; i o = 0; note 2 4.5 to 5.5 -- 490 m a symbol parameter test conditions min. typ. max. unit other v cc (v)
2003 jun 25 13 philips semiconductors product speci?cation 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74hc595; 74hct595 ac characteristics family 74hc gnd = 0 v; t r =t f = 6 ns; c l =50pf. symbol parameter test conditions min. typ. max. unit waveforms v cc (v) t amb =25 c t phl /t plh propagation delay sh_cp to q7 see fig.7 2.0 - 52 160 ns 4.5 - 19 32 ns 6.0 - 15 27 ns propagation delay st_cp to qn see fig.8 2.0 - 55 175 ns 4.5 - 20 35 ns 6.0 - 16 30 ns t phl propagation delay mr to q7 see fig.10 2.0 - 47 175 ns 4.5 - 17 35 ns 6.0 - 14 30 ns t pzh /t pzl 3-state output enable time oe to qn see fig.11 2.0 - 47 150 ns 4.5 - 17 30 ns 6.0 - 14 26 ns t phz /t plz 3-state output disable time oe to qn see fig.11 2.0 - 41 150 ns 4.5 - 15 30 ns 6.0 - 12 26 ns t w shift clock pulse width high or low see fig.7 2.0 75 17 - ns 4.5 15 6 - ns 6.0 13 5 - ns storage clock pulse width high or low see fig.8 2.0 75 11 - ns 4.5 15 4 - ns 6.0 13 3 - ns master reset pulse width low see fig.10 2.0 75 17 - ns 4.5 15 6.0 - ns 6.0 13 5.0 - ns t su set-up time ds to sh_cp see fig.9 2.0 50 11 - ns 4.5 10 4.0 - ns 6.0 9.0 3.0 - ns set-up time sh_cp to st_cp see fig.8 2.0 75 22 - ns 4.5 15 8 - ns 6.0 13 7 - ns t h hold time ds to sh_cp see fig.9 2.0 +3 - 6 - ns 4.5 +3 - 2 - ns 6.0 +3 - 2 - ns
2003 jun 25 14 philips semiconductors product speci?cation 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74hc595; 74hct595 t rem removal time mr to sh_cp see fig.10 2.0 +50 - 19 - ns 4.5 +10 - 7 - ns 6.0 +9 - 6 - ns f max maximum clock pulse frequency sh_cp or st_cp see figs 7 and 8 2.0 9 30 - mhz 4.5 30 91 - mhz 6.0 35 108 - mhz t amb = - 40 to +85 c t phl /t plh propagation delay sh_cp to q7 see fig.7 2.0 -- 200 ns 4.5 -- 40 ns 6.0 -- 34 ns propagation delay st_cp to an see fig.8 2.0 -- 220 ns 4.5 -- 44 ns 6.0 -- 37 ns t phl propagation delay mr to q7 see fig.10 2.0 -- 220 ns 4.5 -- 44 ns 6.0 -- 37 ns t pzh /t pzl 3-state output enable time oe to qn see fig.11 2.0 -- 190 ns 4.5 -- 38 ns 6.0 -- 33 ns t phz /t plz 3-state output disable time oe to qn see fig.11 2.0 -- 190 ns 4.5 -- 38 ns 6.0 -- 33 ns t w shift clock pulse width high or low see fig.7 2.0 95 -- ns 4.5 19 -- ns 6.0 16 -- ns storage clock pulse width high or low see fig.8 2.0 95 -- ns 4.5 19 -- ns 6.0 16 -- ns master reset pulse width low see fig.10 2.0 95 -- ns 4.5 19 -- ns 6.0 16 -- ns t su set-up time ds to sh_cp see fig.9 2.0 65 -- ns 4.5 13 -- ns 6.0 11 -- ns set-up time sh_cp to st_cp see fig.8 2.0 95 -- ns 4.5 19 -- ns 6.0 16 -- ns symbol parameter test conditions min. typ. max. unit waveforms v cc (v)
2003 jun 25 15 philips semiconductors product speci?cation 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74hc595; 74hct595 t h hold time ds to sh_cp see fig.9 2.0 3 -- ns 4.5 3 -- ns 6.0 3 -- ns t rem removal time mr to sh_cp see fig.10 2.0 65 -- ns 4.5 13 -- ns 6.0 11 -- ns f max maximum clock pulse frequency sh_cp or st_cp see figs 7 and 8 2.0 4.8 -- mhz 4.5 24 -- mhz 6.0 28 -- mhz t amb = - 40 to +125 c t phl /t plh propagation delay sh_cp to q7 see fig.7 2.0 -- 240 ns 4.5 -- 48 ns 6.0 -- 41 ns propagation delay st_cp to qn see fig.8 2.0 -- 265 ns 4.5 -- 53 ns 6.0 -- 45 ns t phl propagation delay mr to q7 see fig.10 2.0 -- 265 ns 4.5 -- 53 ns 6.0 -- 45 ns t pzh /t pzl 3-state output enable time oe to qn see fig.11 2.0 -- 225 ns 4.5 -- 45 ns 6.0 -- 38 ns t phz /t plz 3-state output disable time oe to qn see fig.11 2.0 -- 225 ns 4.5 -- 45 ns 6.0 -- 38 ns t w shift clock pulse width high or low see fig.7 2.0 110 -- ns 4.5 22 -- ns 6.0 19 -- ns storage clock pulse width high or low see fig.8 2.0 110 -- ns 4.5 22 -- ns 6.0 19 -- ns master reset pulse width low see fig.10 2.0 110 -- ns 4.5 22 -- ns 6.0 19 -- ns symbol parameter test conditions min. typ. max. unit waveforms v cc (v)
2003 jun 25 16 philips semiconductors product speci?cation 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74hc595; 74hct595 t su set-up time ds to sh_cp see fig.9 2.0 75 -- ns 4.5 15 -- ns 6.0 13 -- ns set-up time sh_cp to st_cp see fig.8 2.0 110 -- ns 4.5 22 -- ns 6.0 19 -- ns t h hold time ds to sh_cp see fig.9 2.0 3 -- ns 4.5 3 -- ns 6.0 3 -- ns t rem removal time mr to sh_cp see fig.10 2.0 75 -- ns 4.5 15 -- ns 6.0 13 -- ns f max maximum clock pulse frequency sh_cp or st_cp see figs 7 and 8 2.0 4 -- mhz 4.5 20 -- mhz 6.0 24 -- mhz symbol parameter test conditions min. typ. max. unit waveforms v cc (v)
2003 jun 25 17 philips semiconductors product speci?cation 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74hc595; 74hct595 family 74hct gnd = 0 v; t r =t f = 6 ns; c l =50pf. symbol parameter test conditions min. typ. max. unit waveforms v cc (v) t amb =25 c t phl /t plh propagation delay sh_cp to q7 see fig.7 4.5 - 25 42 ns propagation delay st_cp to qn see fig.8 4.5 - 24 40 ns t phl propagation delay mr to q7 see fig.10 4.5 - 23 40 ns t pzh /t pzl 3-state output enable time oe to qn see fig.11 4.5 - 21 35 ns t phz /t plz 3-state output disable time oe to qn see fig.11 4.5 - 18 30 ns t w shift clock pulse width high or low see fig.7 4.5 16 6 - ns storage clock pulse width high or low see fig.8 4.5 16 5 - ns master reset pulse width low see fig.10 4.5 20 8 - ns t su set-up time ds to sh_cp see fig.9 4.5 16 5 - ns set-up time sh_cp to st_cp see fig.8 4.5 16 8 - ns t h hold time ds to sh_cp see fig.9 4.5 +3 - 2 - ns t rem removal time mr to sh_cp see fig.10 4.5 +10 - 7 - ns f max maximum clock pulse frequency sh_cp or st_cp see figs 7 and 8 4.5 30 52 - mhz t amb = - 40 to +85 c t phl /t plh propagation delay sh_cp to q7 see fig.7 4.5 -- 53 ns propagation delay st_cp to qn see fig.8 4.5 -- 50 ns t phl propagation delay mr to q7 see fig.10 4.5 -- 50 ns t pzh /t pzl 3-state output enable time oe to qn see fig.11 4.5 -- 44 ns t phz /t plz 3-state output disable time oe to qn see fig.11 4.5 -- 38 ns
2003 jun 25 18 philips semiconductors product speci?cation 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74hc595; 74hct595 t w shift clock pulse width high or low see fig.7 4.5 20 -- ns storage clock pulse width high or low see fig.8 4.5 20 -- ns master reset pulse width low see fig.10 4.5 25 -- ns t su set-up time ds to sh_cp see fig.9 4.5 20 -- ns set-up time sh_cp to st_cp see fig.8 4.5 20 -- ns t h hold time ds to sh_cp see fig.9 4.5 3 -- ns t rem removal time mr to sh_cp see fig.10 4.5 13 -- ns f max maximum clock pulse frequency sh_cp or st_cp see figs 7 and 8 4.5 24 -- mhz t amb = - 40 to +125 c t phl /t plh propagation delay sh_cp to q7 see fig.7 4.5 -- 63 ns propagation delay st_cp to qn see fig.8 4.5 -- 60 ns t phl propagation delay mr to q7 see fig.10 4.5 -- 60 ns t pzh /t pzl 3-state output enable time oe to qn see fig.11 4.5 -- 53 ns t phz /t plz 3-state output disable time oe to qn see fig.11 4.5 -- 45 ns t w shift clock pulse width high or low see fig.7 4.5 24 -- ns storage clock pulse width high or low see fig.8 4.5 24 -- ns master reset pulse width low see fig.10 4.5 30 -- ns t su set-up time ds to sh_cp see fig.9 4.5 24 -- ns set-up time sh_cp to st_cp see fig.8 4.5 24 -- ns t h hold time ds to sh_cp see fig.9 4.5 3 -- ns t rem removal time mr to sh_cp see fig.10 4.5 15 -- ns f max maximum clock pulse frequency sh_cp or st_cp see figs 7 and 8 4.5 20 -- mhz symbol parameter test conditions min. typ. max. unit waveforms v cc (v)
2003 jun 25 19 philips semiconductors product speci?cation 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74hc595; 74hct595 ac waveforms handbook, full pagewidth msa699 t plh t phl t w 1/f max v m v m sh_cp input q7' output t thl t tlh 90% 10% fig.7 waveforms showing the clock (sh_cp) to output (q7) propagation delays, the shift clock pulse width and maximum shift clock frequency. 74hc595: v m = 50%; v i = gnd to v cc . 74hct595: v m = 1.3 v; v i = gnd to 3 v. handbook, full pagewidth msa700 t plh t phl t w 1/f max v m v m v m st_cp input t su sh_cp input qn output fig.8 waveforms showing the storage clock (st_cp) to output (qn) propagation delays, the storage clock pulse width and the shift clock to storage clock set-up time. 74hc595: v m = 50%; v i = gnd to v cc . 74hct595: v m = 1.3 v; v i = gnd to 3 v.
2003 jun 25 20 philips semiconductors product speci?cation 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74hc595; 74hct595 handbook, full pagewidth mlb196 t h t su t h t su q7' output sh_cp input ds input v m v m v m fig.9 waveforms showing the data set-up and hold times for the ds input. 74hc595: v m = 50%; v i = gnd to v cc . 74hct595: v m = 1.3 v; v i = gnd to 3 v. the shaded areas indicate when the input is permitted to change for predictable output performance. handbook, full pagewidth mlb197 t phl t w v m v m v m sh_cp input t rem mr input q7' output fig.10 waveforms showing the master reset ( mr) pulse width, the master reset to output (q7) propagation delay and the master reset to shift clock (sh_cp) removal time. 74hc595: v m = 50%; v i = gnd to v cc . 74hct595: v m = 1.3 v; v i = gnd to 3 v.
2003 jun 25 21 philips semiconductors product speci?cation 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74hc595; 74hct595 handbook, full pagewidth msa697 t plz t phz outputs disabled outputs enabled 90% 10% outputs enabled oe input v m t pzl t pzh v m v m qn output low-to-off off-to-low qn output high-to-off off-to-high t r t f 90% 10% fig.11 waveforms showing the 3-state enable and disable times for input oe. 74hc595: v m = 50%; v i = gnd to v cc . 74hct595: v m = 1.3 v; v i = gnd to 3 v. handbook, full pagewidth mgk563 d.u.t v cc v cc v i v o r t r l = 1 k w c l 50 pf pulse generator fig.12 test circuit for 3-state outputs. definitions for test circuit: r l = load resistor. c l = load capacitance including jig and probe capacitance. r t = termination resistance should be equal to the output impedance z o of the pulse generator. test switch t plh /t phl open t plz /t pzl v cc t phz /t pzh gnd
2003 jun 25 22 philips semiconductors product speci?cation 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74hc595; 74hct595 package outlines references outline version european projection issue date iec jedec jeita sot38-4 95-01-14 03-02-13 m h c (e ) 1 m e a l seating plane a 1 w m b 1 b 2 e d a 2 z 16 1 9 8 e pin 1 index b 0 5 10 mm scale note 1. plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. unit a max. 12 b 1 (1) (1) (1) b 2 cd e e m z h l mm dimensions (inch dimensions are derived from the original mm dimensions) a min. a max. b max. w m e e 1 1.73 1.30 0.53 0.38 0.36 0.23 19.50 18.55 6.48 6.20 3.60 3.05 0.254 2.54 7.62 8.25 7.80 10.0 8.3 0.76 4.2 0.51 3.2 inches 0.068 0.051 0.021 0.015 0.014 0.009 1.25 0.85 0.049 0.033 0.77 0.73 0.26 0.24 0.14 0.12 0.01 0.1 0.3 0.32 0.31 0.39 0.33 0.03 0.17 0.02 0.13 dip16: plastic dual in-line package; 16 leads (300 mil) sot38-4
2003 jun 25 23 philips semiconductors product speci?cation 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74hc595; 74hct595 x w m q a a 1 a 2 b p d h e l p q detail x e z e c l v m a (a ) 3 a 8 9 1 16 y pin 1 index unit a max. a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec jeita mm inches 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 0.7 0.6 0.7 0.3 8 0 o o 0.25 0.1 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 1.0 0.4 sot109-1 99-12-27 03-02-19 076e07 ms-012 0.069 0.010 0.004 0.057 0.049 0.01 0.019 0.014 0.0100 0.0075 0.39 0.38 0.16 0.15 0.05 1.05 0.041 0.244 0.228 0.028 0.020 0.028 0.012 0.01 0.25 0.01 0.004 0.039 0.016 0 2.5 5 mm scale so16: plastic small outline package; 16 leads; body width 3.9 mm sot109-1
2003 jun 25 24 philips semiconductors product speci?cation 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74hc595; 74hct595 unit a 1 a 2 a 3 b p cd (1) e (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec jeita mm 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 1.25 7.9 7.6 1.03 0.63 0.9 0.7 1.00 0.55 8 0 o o 0.13 0.2 0.1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. sot338-1 99-12-27 03-02-19 (1) w m b p d h e e z e c v m a x a y 1 8 16 9 q a a 1 a 2 l p q detail x l (a ) 3 mo-150 pin 1 index 0 2.5 5 mm scale ssop16: plastic shrink small outline package; 16 leads; body width 5.3 mm sot338-1 a max. 2
2003 jun 25 25 philips semiconductors product speci?cation 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74hc595; 74hct595 unit a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.40 0.06 8 0 o o 0.13 0.1 0.2 1 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 sot403-1 mo-153 99-12-27 03-02-18 w m b p d z e 0.25 18 16 9 q a a 1 a 2 l p q detail x l (a ) 3 h e e c v m a x a y 0 2.5 5 mm scale tssop16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm sot403-1 a max. 1.1 pin 1 index
2003 jun 25 26 philips semiconductors product speci?cation 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74hc595; 74hct595 terminal 1 index area 0.5 1 a 1 e h b unit y e 0.2 c references outline version european projection issue date iec jedec jeita mm 3.6 3.4 d h 2.15 1.85 y 1 2.6 2.4 1.15 0.85 e 1 2.5 0.30 0.18 0.05 0.00 0.05 0.1 dimensions (mm are the original dimensions) sot763-1 mo-241 - - - - - - 0.5 0.3 l 0.1 v 0.05 w 0 2.5 5 mm scale sot763-1 dhvqfn16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 x 3.5 x 0.85 mm a (1) max. a a 1 c detail x y y 1 c e l e h d h e e 1 b 27 15 10 9 8 1 16 x d e c b a terminal 1 index area a c c b v m w m e (1) note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. d (1) 02-10-17 03-01-27
2003 jun 25 27 philips semiconductors product speci?cation 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74hc595; 74hct595 data sheet status notes 1. please consult the most recently issued data sheet before initiating or completing a design. 2. the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the latest information is available on the internet at url http://www.semiconductors.philips.com. 3. for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. level data sheet status (1) product status (2)(3) definition i objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. ii preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti?cation (cpcn). definitions short-form specification ? the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition ? limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information ? applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. disclaimers life support applications ? these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes ? philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status production), relevant changes will be communicated via a customer product/process change notification (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
? koninklijke philips electronics n.v. 2003 sca75 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. philips semiconductors C a worldwide company contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales of?ces addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . printed in the netherlands 613508/04/pp 28 date of release: 2003 jun 25 document order number: 9397 750 11263

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